schizoidman@lemm.ee to

RISC-V@lemmy.mlEnglish · 18 hours ago

Chinese RISC-V project teases 2025 debut of advanced chip

www.theregister.com

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Chinese RISC-V project teases 2025 debut of advanced chip

www.theregister.com

schizoidman@lemm.ee to

RISC-V@lemmy.mlEnglish · 18 hours ago

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cross-posted to:
technology@lemmy.world

Third-gen Xiangshan may be close to performance of Arm’s made-for-HPC Neoverse 2

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RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

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